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direct rdram ? page -1 k4r271669b/k4r441869b version 1.11 oct. 2000 october 2000 version 1.11 direct rdram tm 256k x 16/18 bit x 32s banks 128/144mbit rdram(b-die)
direct rdram ? page 0 k4r271669b/k4r441869b version 1.11 oct. 2000 change history version 1.11 ( october 2000) - preliminary * based on the rambus 1.11ver. 128/144mbit(32s banks) rdram datasheet.
direct rdram ? page 1 k4r271669b/k4r441869b version 1.11 oct. 2000 overview the rambus direct rdram? is a general purpose high- performance memory device suitable for use in a broad range of applications including computer memory, graphics, video, and any other application where high bandwidth and low latency are required. the 128/144-mbit direct rambus drams (rdram a ) are extremely high-speed cmos drams organized as 8m words by 16 or 18 bits. the use of rambus signaling level (rsl) technology permits 600mhz to 800mhz transfer rates while using conventional system and board design technologies. direct rdram devices are capable of sustained data transfers at 1.25 ns per two bytes (10ns per sixteen bytes). the architecture of the direct rdrams allows the highest sustained bandwidth for multiple, simultaneous randomly addressed memory transactions. the separate control and data buses with independent row and column control yield over 95% bus efficiency. the direct rdram's 32 banks support up to four simultaneous transactions. system oriented features for mobile, graphics and large memory systems include power management, byte masking, and x18 organization. the two data bits in the x18 organiza- tion are general and can be used for additional storage and bandwidth or for error correction. features highest sustained bandwidth per dram device - 1.6gb/s sustained data transfer rate - separate control and data buses for maximized efficiency - separate row and column control buses for easy scheduling and highest performance - 32 banks: four transactions can take place simul- taneously at full bandwidth data rates low latency features - write buffer to reduce read latency - 3 precharge mechanisms for controller flexibility - interleaved transactions advanced power management: - direct rdram operates from a 2.5 volt supply - multiple low power states allows flexibility in power consumption versus time to transition to active state - power-down self-refresh organization: 1kbyte pages and 32 banks, x 16/18 - x18 organization allows ecc configurations or increased storage/bandwidth - x16 organization for low cost applications uses rambus signaling level (rsl) for up to 800mhz operation the 128/144-mbit direct rdrams are offered in a csp horizontal package suitable for desktop as well as low- profile add-in card and mobile applications. key timing parameters/part numbers a. ? 32s ? - 32 banks which use a ? split ? bank architecture . b. ? n ? - normal package, ? m ? - mirrored package. c. ? c ? - rdram core uses normal power self refresh. figure 1: direct rdram csp package organization speed part number bin i/o freq. mhz t rac (row access time) ns 256kx16x32s a -ck8 800 45 k4r271669b-n b (m)c c k8 -ck7 711 45 k4r271669b-n(m)ck7 -cg6 600 53.3 k4r271669b-n(m)cg6 256kx18x32s a -ck8 800 45 k4r441869b-n(m)ck8 -ck7 711 45 k4r441869b-n(m)ck7 -cg6 600 53.3 k4r441869b-n(m)cg6 a. normal package b. mirrored package k4r xxxx 69b- n xxx samsung 050 m k4r xxxx 69b- m xxx samsung 050
direct rdram ? page 2 k4r271669b/k4r441869b version 1.11 oct. 2000 pinouts and definitions center-bonded devices these tables shows the pin assignments of the center-bonded rdram package. the top table is for the normal package, and bottom table is for the mirrored package. the mechan- ical dimensions of this package are shown in a later section. refer to section "center-bonded ubga package" on page 18. table 1-1: a. center-bonded device (top view for normal package) 12 gnd vdd vdd gnd 11 10 dqa7 dqa4 cfm cfmn rq5 rq3 dqb0 dqb4 dqb7 9 gnd vdd gnd gnda vdd gnd vdd vdd gnd 8 cmd dqa5 dqa2 vdda rq6 rq2 dqb1 dqb5 sio1 7 6 5 sck dqa6 dqa1 vref rq7 rq1 dqb2 dqb6 sio0 4 vcmos gnd vdd gnd gnd vdd gnd gnd vcmos 3 dqa8 * dqa3 dqa0 ctmn ctm rq4 rq0 dqb3 dqb8 * 2 1 gnd vdd vdd gnd a b c d e f g h j table 1-2: a. center-bonded device (top view for mirrored package) 12 gnd vdd vdd gnd 11 10 dqa8 * dqa3 dqa0 ctmn ctm rq4 rq0 dqb3 dqb8 * 9 vcmos gnd vdd gnd gnd vdd gnd gnd vcmos 8 sck dqa6 dqa1 vref rq7 rq1 dqb2 dqb6 sio0 7 6 5 cmd dqa5 dqa2 vdda rq6 rq2 dqb1 dqb5 sio1 4 gnd vdd gnd gnda vdd gnd vdd vdd gnd 3 dqa7 dqa4 cfm cfmn rq5 rq3 dqb0 dqb4 dqb7 2 1 gnd vdd vdd gnd a b c d e f g h j for normal package, pin #1(row 1, col a) is located at the a1 position on the top side and the a1 position is marked by the marker ? ? . for mirrored package, pin #1(row 1, col a) is located at the a1 postion on the top side and the a1 position is marked by the alphabet ? m ? . chip top view * dqa8/dqb8 are ju st used for 144mb rdram. these two pins are nc(no connection) in 128mb rdram. b. top marking example of normal package b. top marking example of mirrored package col row col row k4r xxxx 69b- n xxx samsung 050 m k4r xxxx 69b- m xxx samsung 050
direct rdram ? page 3 k4r271669b/k4r441869b version 1.11 oct. 2000 table 2: pin description signal i/o type # of pins description sio1,sio0 i/o cmos a 2 serial input/output. pins for reading from and writing to the control regis- ters using a serial access protocol. also used for power management. cmd i cmos a 1 command input. pins used in conjunction with sio0 and sio1 for reading from and writing to the control registers. also used for power manage- ment . sck i cmos a 1 serial clock input. clock source used for reading from and writing to the control registers v dd 10 supply voltage for the rdram core and interface logic. v dda 1 supply voltage for the rdram analog circuitry. v cmos 2 supply voltage for cmos input/output pins . gnd 13 ground reference for rdram core and interface. gnda 1 ground reference for rdram analog circuitry. dqa8..dqa0 i/o rsl b 9 data byte a. nine pins which carry a byte of read or write data between the channel and the rdram. dqa8 is not used (no connection) by rdrams with a x16 organization. cfm i rsl b 1 clock from master. interface clock used for receiving rsl signals from the channel. positive polarity. cfmn i rsl b 1 clock from master. interface clock used for receiving rsl signals from the channel. negative polarity v ref 1 logic threshold reference voltage for rsl signals ctmn i rsl b 1 clock to master. interface clock used for transmitting rsl signals to the channel. negative polarity. ctm i rsl b 1 clock to master. interface clock used for transmitting rsl signals to the channel. positive polarity. rq7..rq5 or row2..row0 i rsl b 3 row access control. three pins containing control and address informa- tion for row accesses. rq4..rq0 or col4..col0 i rsl b 5 column access control. five pins containing control and address informa- tion for column accesses. dqb8.. dqb0 i/o rsl b 9 data byte b. nine pins which carry a byte of read or write data between the channel and the rdram. dqb8 is not used (no connection) by rdrams with a x16 organization. total pin count per package 62 a. all cmos signals are high-true; a high voltage is a logic one and a low voltage is logic zero. b. all rsl signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
direct rdram ? page 4 k4r271669b/k4r441869b version 1.11 oct. 2000 figure 2: 128/144 mbit(256k x16/18 x32s) direct rdram block diagram bank 31 dqa8..dqa0 1 : 8 d e m u x 8 : 1 m u x w r i t e b u f f e r 1 : 8 d e m u x w r i t e b u f f e r 8 : 1 m u x bank 30 bank 29 bank 18 bank 17 bank 16 bank 15 bank 14 bank 13 bank 1 bank 0 s a m p 1 / 2 dqb8..dqb0 9 1:8 demux 1:8 demux packet decode 9 5 3 row2..row0 col4..col0 ctm ctmn cfm cfmn 2 sck,cmd rclk tclk control registers dc cop c bc ma mb dx xop bx dr r rop br 8 8 6 5 5 5 5 5 6 9 5 5 11 av m s write buffer match match mux match devid 512x64x144 internal dqb data path column decode & mask 72 9 9 72 9 dm refr row decode mux act rd, wr power modes dram core mux xop decode prex prec 9 9 9 9 72 9 9 9 prer colx colc colm 2 sio0,sio1 sense amp internal dqa data path packet decode rowa rowr rclk rclk r c l k t c l k r c l k t c l k rq7..rq5 or rq4..rq0 or s a m p 0 / 1 s a m p 0 s a m p 1 4 / 1 5 s a m p 1 5 s a m p 1 3 / 1 4 s a m p 1 6 / 1 7 s a m p 1 7 / 1 8 s a m p 1 6 s a m p 2 9 / 3 0 s a m p 3 0 / 3 1 s a m p 3 1 32x72 s a m p 1 / 2 72 s a m p 0 / 1 s a m p 0 s a m p 1 4 / 1 5 s a m p 1 5 s a m p 1 3 / 1 4 s a m p 1 6 / 1 7 s a m p 1 7 / 1 8 s a m p 1 6 s a m p 2 9 / 3 0 s a m p 3 0 / 3 1 s a m p 3 1 32x72 32x72 bank 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
direct rdram ? page 5 k4r271669b/k4r441869b version 1.11 oct. 2000 general description figure2 is a block diagram of the 128/144mbit direct rdram. it consists of two major blocks: a ? core ? block built from banks and sense amps similar to those found in other types of dram, and a direct rambus interface block which permits an external controller to access this core at up to 1.6gb/s. control registers: the cmd, sck, sio0, and sio1 pins appear in the upper center of figure2. they are used to write and read a block of control registers. these registers supply the rdram configuration information to a controller and they select the operating modes of the device. the nine bit refr value is used for tracking the last refreshed row. most importantly, the five bit devid speci- fies the device address of the rdram on the channel. clocking: the ctm and ctmn pins (clock-to-master) generate tclk (transmit clock), the internal clock used to transmit read data. the cfm and cfmn pins (clock-from- master) generate rclk (receive clock), the internal clock signal used to receive write data and to receive the row and col pins. dqa,dqb pins: these 18 pins carry read (q) and write (d) data across the channel. they are multiplexed/de-multi- plexed from/to two 72-bit data paths (running at one-eighth the data frequency) inside the rdram. banks: the 16mbyte core of the rdram is divided into thirty two 0.5mbyte banks, each organized as 512 rows, with each row containing 64 dualocts, and each dualoct containing 16 bytes. a dualoct is the smallest unit of data that can be addressed. sense amps: the rdram contains 34 sense amps. each sense amp consists of 512 bytes of fast storage (256 for dqa and 256 for dqb) and can hold one-half of one row of one bank of the rdram. the sense amp may hold any of the 512 half-rows of an associated bank. however, each sense amp is shared between two adjacent banks of the rdram (except for sense amps 0, 15, 16, and 31). this introduces the restriction that adjacent banks may not be simultaneously accessed. rq pins: these pins carry control and address informa- tion. they are broken into two groups. rq7..rq5 are also called row2..row0, and are used primarily for controlling row accesses. rq4..rq0 are also called col4..col0, and are used primarily for controlling column accesses. row pins: the principle use of these three pins is to manage the transfer of data between the banks and the sense amps of the rdram. these pins are de-multiplexed into a 24-bit rowa (row-activate) or rowr (row-operation) packet. col pins: the principle use of these five pins is to manage the transfer of data between the dqa/dqb pins and the sense amps of the rdram. these pins are de-multi- plexed into a 23-bit colc (column-operation) packet and either a 17-bit colm (mask) packet or a 17-bit colx (extended-operation) packet. act command: an act (activate) command from an rowa packet causes one of the 512 rows of the selected bank to be loaded to its associated sense amps (two 256 byte sense amps for dqa and two for dqb). prer command: a prer (precharge) command from an rowr packet causes the selected bank to release its two associated sense amps, permitting a different row in that bank to be activated, or permitting adjacent banks to be acti- vated. rd command: the rd (read) command causes one of the 64 dualocts of one of the sense amps to be transmitted on the dqa/dqb pins of the channel. wr command: the wr (write) command causes a dualoct received from the dqa/dqb data pins of the channel to be loaded into the write buffer. there is also space in the write buffer for the bc bank address and c column address information. the data in the write buffer is automatically retired (written with optional bytemask) to one of the 64 dualocts of one of the sense amps during a subse- quent cop command. a retire can take place during a rd, wr, or nocop to another device, or during a wr or nocop to the same device. the write buffer will not retire during a rd to the same device. the write buffer reduces the delay needed for the internal dqa/dqb data path turn- around. prec precharge: the prec, rda and wra commands are similar to nocop, rd and wr, except that a precharge operation is performed at the end of the column operation. these commands provide a second mechanism for performing precharge. prex precharge: after a rd command, or after a wr command with no byte masking (m=0), a colx packet may be used to specify an extended operation (xop). the most important xop command is prex. this command provides a third mechanism for performing precharge.
direct rdram ? page 6 k4r271669b/k4r441869b version 1.11 oct. 2000 packet format figure3 shows the formats of the rowa and rowr packets on the row pins. table3 describes the fields which comprise these packets. dr4t and dr4f bits are encoded to contain both the dr4 device address bit and a framing bit which allows the rowa or rowr packet to be recognized by the rdram. the av (rowa/rowr packet selection) bit distinguishes between the two packet types. both the rowa and rowr packet provide a five bit device address and a five bit bank address. an rowa packet uses the remaining bits to specify a nine bit row address, and the rowr packet uses the remaining bits for an eleven bit opcode field. note the use of the ? rsvx ? notation to reserve bits for future address field extension. figure3 also shows the formats of the colc, colm, and colx packets on the col pins. table4 describes the fields which comprise these packets. the colc packet uses the s (start) bit for framing. a colm or colx packet is aligned with this colc packet, and is also framed by the s bit. the 23 bit colc packet has a five bit device address, a five bit bank address, a six bit column address, and a four bit opcode. the colc packet specifies a read or write command, as well as some power management commands. the remaining 17 bits are interpreted as a colm (m=1) or colx (m=0) packet. a colm packet is used for a colc write command which needs bytemask control. the colm packet is associated with the colc packet from at least t rtr earlier. an colx packet may be used to specify an indepen- dent precharge command. it contains a five bit device address, a five bit bank address, and a five bit opcode. the colx packet may also be used to specify some house- keeping and power management commands. the colx packet is framed within a colc packet but is not otherwise associated with any other packet. table 3: field description for rowa packet and rowr packet field description dr4t,dr4f bits for framing (recognizing) a rowa or rowr packet. also encodes highest device address bit. dr3..dr0 device address for rowa or rowr packet. br4..br0 bank address for rowa or rowr packet. rsvb denotes bits ignored by the rdram. av selects between rowa packet (av=1) and rowr packet (av=0). r8..r0 row address for rowa packet. rsvr denotes bits ignored by the rdram. rop10..rop0 opcode field for rowr packet. specifies precharge, refresh, and power management functions. table 4: field description for colc packet, colm packet, and colx packet field description s bit for framing (recognizing) a colc packet, and indirectly for framing colm and colx packets. dc4..dc0 device address for colc packet. bc4..bc0 bank address for colc packet. rsvb denotes bits reserved for future extension (controller drives 0?s). c5..c0 column address for colc packet. rsvc denotes bits ignored by the rdram. cop3..cop0 opcode field for colc packet. specifies read, write, precharge, and power management functions. m selects between colm packet (m=1) and colx packet (m=0). ma7..ma0 bytemask write control bits. 1=write, 0=no-write. ma0 controls the earliest byte on dqa8..0. mb7..mb0 bytemask write control bits. 1=write, 0=no-write. mb0 controls the earliest byte on dqb8..0. dx4..dx0 device address for colx packet. bx4..bx0 bank address for colx packet. rsvb denotes bits reserved for future extension (controller drives 0?s). xop4..xop0 opcode field for colx packet. specifies precharge, i ol control, and power management functions.
direct rdram ? page 7 k4r271669b/k4r441869b version 1.11 oct. 2000 figure 3: packet formats ctm/cfm col4 col3 col2 col1 col0 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 8 t 9 t 10 t 11 t 0 t 1 t 2 t 3 t 0 t 1 t 2 t 3 s=1 a ma7 ma5 ma3 ma1 m=1 ma6 ma4 ma2 ma0 mb7 mb4 mb1 mb6 mb3 mb0 mb5 mb2 r2 ctm/cfm row2 dr4t dr2 br0 br3 rsvr r8 r5 row1 dr4f dr1 br1 br4 rsvr r7 r4 r1 row0 dr3 dr0 br2 rsvb av=1 r6 r3 r0 act a0 prex d0 msk (b1) prer c0 wr b1 c4 ctm/cfm col4 dc4 s=1 rsvc col3 dc3 c5 c3 col2 dc2 cop1 rsvb bc2 c2 dc1 cop0 bc4 bc1 c1 dc0 cop2 cop3 bc3 bc0 c0 col1 col0 ctm/cfm row2 row1 row0 ctm/cfm col4 col3 col2 col1 col0 rop2 dr4t dr2 br0 br3 rop10 rop8 rop5 dr4f dr1 br1 br4 rop9 rop7 rop4 rop1 dr3 dr0 br2 rsvb av=0 rop6 rop3 rop0 s=1 b dx4 xop4 rsvb bx1 m=0 dx3 xop3 bx4 bx0 dx2 xop2 bx3 dx1 xop1 bx2 dx0 xop0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 rowa packet colm packet colc packet colx packet rowr packet ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t packet a the colm is associated with a previous colc, and is aligned with the present colc, indicated by the start bit (s=1) position. b the colx is aligned with the present colc, indicated by the start bit (s=1) position.
direct rdram ? page 8 k4r271669b/k4r441869b version 1.11 oct. 2000 field encoding summary table5 shows how the six device address bits are decoded for the rowa and rowr packets. the dr4t and dr4f encoding merges a fifth device bit with a framing bit. when neither bit is asserted, the device is not selected. note that a broadcast operation is indicated when both bits are set. broadcast operation would typically be used for refresh and power management commands. if the device is selected, the dm (devicematch) signal is asserted and an act or rop command is performed. table6 shows the encodings of the remaining fields of the rowa and rowr packets. an rowa packet is specified by asserting the av bit. this causes the specified row of the specified bank of this device to be loaded into the associated sense amps. an rowr packet is specified when av is not asserted. an 11 bit opcode field encodes a command for one of the banks of this device. the prer command causes a bank and its two associated sense amps to precharge, so another row or an adjacent bank may be activated. the refa (refresh-acti- vate) command is similar to the act command, except the row address comes from an internal register refr, and refr is incremented at the largest bank address. the refp (refresh-precharge) command is identical to a prer command. the napr, naprc, pdnr, attn, and rlxr commands are used for managing the power dissipation of the rdram and are described in more detail in ? power state manage- ment ? on page 50. the tcen and tcal commands are used to adjust the output driver slew rate and they are described in more detail in ? current and temperature control ? on page 56. table 5: device field encodings for rowa packet and rowr packet dr4t dr4f device selection device match signal (dm) 1 1 all devices (broadcast) dm is set to 1 0 1 one device selected dm is set to 1 if {devid4..devid0} == {0,dr3..dr0} else dm is set to 0 1 0 one device selected dm is set to 1 if {devid4..devid0} == {1,dr3..dr0} else dm is set to 0 0 0 no packet present dm is set to 0 table 6: rowa packet and rowr packet field encodings dm a av rop10..rop0 field name command description 10 9 8 7 6 5 4 3 2:0 0 - - - - - - - - - --- - no operation. 1 1 row address act activate row r8..r0 of bank br4..br0 of device and move device to attn b . 1 0 1 1 0 0 0 x c x x 000 prer precharge bank br4..br0 of this device. 1 0 0 0 0 1 1 0 0 x 000 refa refresh (activate) row refr8..refr0 of bank br4..br0 of device. increment refr if br4..br0 = 11111 (see figure51). 1 0 1 0 1 0 1 0 0 x 000 refp precharge bank br4..br0 of this device after refa (see figure51). 1 0 x x 0 0 0 0 1 x 000 pdnr move this device into the powerdown (pdn) power state (see figure48). 1 0 x x 0 0 0 1 0 x 000 napr move this device into the nap (nap) power state (see figure48). 1 0 x x 0 0 0 1 1 x 000 naprc move this device into the nap (nap) power state conditionally 1 0 x x x x x x x 0 000 attn b move this device into the attention (attn) power state (see figure46). 1 0 x x x x x x x 1 000 rlxr move this device into the standby (stby) power state (see figure47). 1 0 0 0 0 0 0 0 0 x 001 tcal temperature calibrate this device (see figure54). 1 0 0 0 0 0 0 0 0 x 010 tcen temperature calibrate/enable this device (see figure54). 1 0 0 0 0 0 0 0 0 0 000 norop no operation. a. the dm (device match signal) value is determined by the dr4t,dr4f, dr3..dr0 field of the rowa and rowr packets. see table5. b. the attn command does not cause a rlx-to-attn transition for a broadcast operation (dr4t/dr4f=1/1). c. an ? x ? entry indicates which commands may be combined. for instance, the three commands prer/naprc/rlxr may be specified in one rop val ue (011000111000).
direct rdram ? page 9 k4r271669b/k4r441869b version 1.11 oct. 2000 table7 shows the cop field encoding. the device must be in the attn power state in order to receive colc packets. the colc packet is used primarily to specify rd (read) and wr (write) commands. retire operations (moving data from the write buffer to a sense amp) happen automatically. see figure18 for a more detailed description. the colc packet can also specify a prec command, which precharges a bank and its associated sense amps. the rda/wra commands are equivalent to combining rd/wr with a prec. rlxc (relax) performs a power mode transi- tion. see ? power state management ? on page 50. table8 shows the colm and colx field encodings. the m bit is asserted to specify a colm packet with two 8 bit bytemask fields ma and mb. if the m bit is not asserted, an colx is specified. it has device and bank address fields, and an opcode field. the primary use of the colx packet is to permit an independent prex (precharge) command to be specified without consuming control bandwidth on the row pins. it is also used for the cal(calibrate) and sam (sample) current control commands (see ? current and temperature control ? on page 56), and for the rlxx power mode command (see ? power state management ? on page 50). table 7: colc packet field encodings s dc4.. dc0 (select device) a cop3..0 name command description 0 ---- ----- - no operation. 1 /= (devid4 ..0) ----- - retire write buffer of this device. 1 == (devid4 ..0) x000 b nocop retire write buffer of this device. 1 == (devid4 ..0) x001 wr retire write buffer of this device, then write column c5..c0 of bank bc4..bc0 to write buffer. 1 == (devid4 ..0) x010 rsrv reserved, no operation. 1 == (devid4 ..0) x011 rd read column c5..c0 of bank bc4..bc0 of this device. 1 == (devid4 ..0) x100 prec retire write buffer of this device, then precharge bank bc4..bc0 (see figure15). 1 == (devid4 ..0) x101 wra same as wr, but precharge bank bc4..bc0 after write buffer (with new data) is retired. 1 == (devid4 ..0) x110 rsrv reserved, no operation. 1 == (devid4 ..0) x111 rda same as rd, but precharge bank bc4..bc0 afterward. 1 == (devid4 ..0) 1xxx rlxc move this device into the standby (stby) power state (see figure47). a. ? /= ? means not equal, ? == ? means equal. b. an ? x ? entry indicates which commands may be combined. for instance, the two commands wr/rlxc may be specified in one cop value (1001). table 8: colm packet and colx packet field encodings m dx4 .. dx0 (selects device) xop4..0 name command description 1 ---- - msk mb/ma bytemasks used by wr/wra. 0 /= (devid4 ..0) - - no operation. 0 == (devid4 ..0) 00000 noxop no operation. 0 == (devid4 ..0) 1xxx0 a prex precharge bank bx4..bx0 of this device (see figure15). 0 == (devid4 ..0) x10x0 cal calibrate (drive) i ol current for this device (see figure53). 0 == (devid4 ..0) x11x0 cal/sam calibrate (drive) and sample ( update) i ol current for this device (see figure53). 0 == (devid4 ..0) xxx10 rlxx move this device into the standby (stby) power state (see figure47). 0 == (devid4 ..0) xxxx1 rsrv reserved, no operation. a. an ? x ? entry indicates which commands may be combined. for instance, the two commands prex/rlxx may be specified in one xop value (1001 0).
direct rdram ? page 10 k4r271669b/k4r441869b version 1.11 oct. 2000 electrical conditions table 9: electrical conditions symbol parameter and conditions min max unit t j junction temperature under bias - 100 c v dd, v dda supply voltage 2.50 - 0.13 2.50 + 0.13 v v dd,n, v dda,n supply voltage droop (dc) during nap interval (t nlimit ) - 2.0 % v dd,n, v dda,n supply voltage ripple (ac) during nap interval (t nlimit ) -2.0 2.0 % v cmos a supply voltage for cmos pins (2.5v controllers) supply voltage for cmos pins (1.8v controllers) v dd 1.80 - 0.1 v dd 1.80 + 0.2 v v v ref reference voltage 1.40 - 0.2 1.40 + 0.2 v v dil rsl data input - low voltage v ref - 0.5 v ref - 0.2 v v dih rsl data input - high voltage b v ref + 0.2 v ref + 0.5 v r da rsl data asymmetry: r da = (v dih - v ref ) / (v ref - v dil ) 0.67 1.00 - v cm rsl clock input - common mode v cm = (v cih +v cil) /2 1.3 1.8 v v cis,ctm rsl clock input swing: v cis = v cih - v cil (ctm,ctmn pins). 0.35 1.00 v v cis,cfm rsl clock input swing: v cis = v cih - v cil (cfm,cfmn pins). 0.225 1.00 v v il,cmos cmos input low voltage - 0.3 c v cmos /2 - 0.25 v v ih,cmos cmos input high voltage v cmos /2 + 0.25 v cmos +0.3 d v a. v cmos must remain on as long as v dd is applied and cannot be turned off. b. v dih is typically equal to v term (1.8v 0.1v) under dc conditions in a system. c. voltage undershoot is limited to -0.7v for a duration of less than 5ns. d. voltage overshoot is limited tov cmos +0.7v for a duration of less than 5ns
direct rdram ? page 11 k4r271669b/k4r441869b version 1.11 oct. 2000 electrical characteristics table 10: electrical characteristics symbol parameter and conditions min max unit q jc junction-to-case thermal resistance - 0.5 c/watt i ref v ref current @ v ref,max -10 10 m a i oh rsl output high current @ (0 v out v dd ) -10 10 m a i all rsl i ol current @ v ol = 0.9v, v dd,min , t j,max a a. this measurement is made in manual current control mode; i.e. with all output device leg s sinking current. 30.0 90.0 ma d i ol rsl i ol current resolution ste p - 2.0 ma r out dynamic output impedance @ v ol = 0.9v 150 - w i ol rsl i ol current @ v ol = 1.0v b , c b. this measurement is made in automatic c urrent control mode after at least 64 current control calibration operations to a device and after cca and ccb are initialized to a value of 64. this value applies to all dqa and dqb pins. c. this measurement is made in automatic c urrent control mode in a 25 w test system with v term = 1.714v and v ref = 1.357v and with the asyma and asymb register fields set to 0. 26.6 30.6 ma i i,cmos cmos input leakage current @ (0 v i,cmos v cmos ) -10.0 10.0 m a v ol,cmos cmos output voltage @ i ol,cmos = 1.0ma - 0.3 v v oh,cmos cmos output high voltage @ i oh,cmos = -0.25ma v cmos -0.3 - v
direct rdram ? page 12 k4r271669b/k4r441869b version 1.11 oct. 2000 timing conditions table 11: timing conditions symbol parameter min max unit figure(s) t cycle ctm and cfm cycle times (-800) 2.50 3.83 ns figure55 ctm and cfm cycle times (-711) 2.80 3.83 ctm and cfm cycle times (-600) 3.33 3.83 t cr , t cf ctm and cfm input rise and fall times. use the minimum value of these parameters during testing. 0.2 0.5 ns figure55 t ch , t cl ctm and cfm high and low times 40% 60% t cycle figure55 t tr ctm-cfm differential (mse/ms=0/0) ctm-cfm differential (mse/ms=1/1) 0.0 0.9 1.0 1.0 t cycle figure43 figure55 t dcw domain crossing window -0.1 0.1 t cycle figure61 t dr , t df dqa/dqb/row/col input rise/fall times (20% to 80%). use the minimum value of these parameters during testing. 0.2 0.65 ns figure56 t s , t h dqa/dqb/row/col-to-cfm set/hold @ t cycle =2.50ns dqa/dqb/row/col-to-cfm set/hold @ t cycle =2.81ns dqa/dqb/row/col-to-cfm set/hold @ t cycle =3.33ns 0.200 b 0.240 c,d 0.275 b,d - - - ns figure56 t dr1, t df1 sio0, sio1 input rise and fall times - 5.0 ns figure58 t dr2, t df2 cmd, sck input rise and fall times - 2.0 ns figure58 t cycle1 sck cycle time - serial control register transactions 1000 - ns figure58 sck cycle time - power transitions 10 - ns figure58 t ch1 , t cl1 sck high and low times 4.25 - ns figure58 t s1 cmd setup time to sck rising or falling edge e 1.25 - ns figure58 t h1 cmd hold time to sck rising or falling edge e 1 - ns figure58 t s2 sio0 setup time to sck falling edge 40 - ns figure58 t h2 sio0 hold time to sck falling edge 40 - ns figure58 t s3 pdev setup time on dqa5..0 to sck rising edge. 0 - ns figure49 t h3 pdev hold time on dqa5..0 to sck rising edge. 5.5 - ns figure59 t s4 row2..0, col4..0 setup time for quiet window -1 - t cycle figure49 t h4 row2..0, col4..0 hold time for quiet window f 5 - t cycle figure49 t npq quiet on row/col bits during nap/pdn entry 4 - t cycle figure48 t readtocc offset between read data and cc packets (same device) 12 - t cycle figure53 t ccsamtoread offset between cc packet and read data (same device) 8 - t cycle figure53 t ce ctm/cfm stable before nap/pdn exit 2 - t cycle figure49 t cd ctm/cfm stable after nap/pdn entry 100 - t cycle figure48 t frm row packet to col packet attn framing delay 7 - t cycle figure47 t nlimit maximum time in nap mode 10.0 m s figure46
direct rdram ? page 13 k4r271669b/k4r441869b version 1.11 oct. 2000 a. mse/ms are fields of the skip register. for this combination (skip override) the tdcw parameter range is effectively 0.0 to 0 .0. b. this parameter also applies to a -800 or -711 part when operated with t cycle =3.33ns. c. t s,min and t h,min for other t cycle values can be interpolated between or extrapolated from the timings at the 3 specified t cycle values. d. this parameter also applies to a -800 part when operated with t cycle =2.81ns. e. with v il,cmos =0.5v cmos -0.4v and v ih,cmos =0.5v cmos +0.4v f. effective hold becomes t h4 ?=t h4 +[pdnxa ? 64 ? t scycle +t pdnxb,max ]-[pdnx ? 256?t scycle ] if [pdnx ? 256 ? t scycle ] < [pdnxa ? 64 ? t scycle +t pdnxb,max ]. see figure49 . t ref refresh interval 32 ms figure51 t burst interval after pdn or nap (with self-refresh) exit in which all banks of the rdram must be refreshed at least once. 200 m s figure52 t cctrl current control interval 34 t cycle 100ms ms/t cycle figure53 t temp temperature control interval 100 ms figure54 t tcen tce command to tcal command 150 - t cycle figure54 t tcal tcal command to quiet window 2 2 t cycle figure54 t tcquiet quiet window (no read data) 140 - t cycle figure54 t pause rdram delay (no rsl operations allowed) 200.0 m s page 38 table 11: timing conditions symbol parameter min max unit figure(s)
direct rdram ? page 14 k4r271669b/k4r441869b version 1.11 oct. 2000 timing characteristics table 12: timing characteristics symbol parameter min max unit figure(s) t q ctm-to-dqa/dqb output time @ t cycle =2.50ns -0.260 a +0.260 a ns figure57 ctm-to-dqa/dqb output time @ t cycle =2.81ns -0.300 a, b +0.300 a,b ctm-to-dqa/dqb output time @ t cycle =3.33ns 0.350 a, c +0.350 a ,c t qr , t qf dqa/dqb output rise and fall times 0.2 0.45 ns figure57 t q1 sck(neg)-to-sio0 delay @ c load,max = 20pf (sd read data valid). - 10 ns figure60 t hr sck(pos)-to-sio0 delay @ c load,max = 20pf (sd read data hold). 2 - ns figure60 t qr1 , t qf1 sio out rise/fall @ c load,max = 20pf - 5 ns figure60 t prop1 sio0-to-sio1 or sio1-to-sio0 delay @ c load,max = 20pf - 10 ns figure60 t napxa nap exit delay - phase a - 50 ns figure49 t napxb nap exit delay - phase b - 40 ns figure49 t pdnxa pdn exit delay - phase a - 4 m s figure49 t pdnxb pdn exit delay - phase b - 9000 t cycle figure49 t as attn-to-stby power state delay - 1 t cycle figure47 t sa stby-to-attn power state delay - 0 t cycle figure47 t asn attn/stby-to-nap power state delay - 8 t cycle figure48 t asp attn/stby-to-pdn power state delay - 8 t cycle figure48 a. t q,min and t q,max f or other t cycle values can be i nterpolat ed b etween or extrapolat ed f rom the timings at the 3 specified t cycle values. b. this parameter also a pplies to a -800 part when operated with t cycle = 2.81n s . c. this parameter also applies to a -800 or -711 part when operated with t cycle =3.33ns.
direct rdram ? page 15 k4r271669b/k4r441869b version 1.11 oct. 2000 timing parameters table 13: timing parameter summary parameter description min -45 -800 min -45 -711 min -53.3 -600 max units figure(s) t rc row cycle time of rdram banks -the interval between rowa packets with act commands to the same bank. 28 28 28 - t cycle figure16 figure17 t ras ras-asserted time of rdram bank - the interval between rowa packet with act command and next rowr packet with prer a command to the same bank. 20 20 20 64 m s b t cycle figure16 figure17 t rp row precharge time of rdram banks - the interval between rowr packet with prer a command and next rowa packet with act command to the same bank. 8 8 8 - t cycle figure16 figure17 t pp precharge-to-precharge time of rdram device - the interval between succes- sive rowr packets with prer a commands to any banks of the same device. 8 8 8 - t cycle figure13 t rr ras-to-ras time of rdram device - the interval between successive rowa packets with act commands to any banks of the same device. 8 8 8 - t cycle figure14 t rcd ras-to-cas delay - the interval from rowa packet with act command to colc packet with rd or wr command). note - the ras-to-cas delay seen by the rdram core (t rcd-c ) is equal to t rcd-c = 1 + t rcd because of differ- ences in the row and column paths through the rdram interface. 9 7 7 - t cycle figure16 figure17 t cac cas access delay - the interval from rd command to q read data. the equa- tion for t cac is given in the tparm register in figure40. 8 8 8 12 t cycle figure5 figure40 t cwd cas write delay (interval from wr command to d write data. 6 6 6 6 t cycle figure5 t cc cas-to-cas time of rdram bank - the interval between successive colc commands). 4 4 4 - t cycle figure16 figure17 t packet length of rowa, rowr, colc, colm or colx packet. 4 4 4 4 t cycle figure3 t rtr interval from colc packet with wr command to colc packet which causes retire, and to colm packet with bytemask. 8 8 8 - t cycle figure18 t offp the interval (offset) from colc packet with rda command, or from colc packet with retire command (after wra automatic precharge), or from colc packet with prec command, or from colx packet with prex command to the equivalent rowr packet with prer. the equation for t offp is given in the tparm register in figure40. 4 4 4 4 t cycle figure15 figure40 t rdp interval from last colc packet with rd command to rowr packet with prer. 4 4 4 - t cycle figure16 t rtp interval from last colc packet with automatic retire command to rowr packet with prer. 4 4 4 - t cycle figure17 a. or equivalent prec or prex command. see figure15. b. this is a constraint imposed by the core, and is therefore in units of m s rather than t cycle .
direct rdram ? page 16 k4r271669b/k4r441869b version 1.11 oct. 2000 absolute maximum ratings i dd - supply current profile table 14: absolute maximum ratings symbol parameter min max unit v i,abs voltage applied to any rsl or cmos pin with respect to gnd - 0.3 v dd +0.3 v v dd,abs , v dda,abs voltage on vdd and vdda with respect to gnd - 0.5 v dd +1.0 v t store storage temperature - 50 100 c table 15: supply current profile i dd value rdram power state and steady-state transaction rates a min max -45 -800 max -45 -711 max -53.3 -600 unit i dd,pdn device in pdn, self-refresh enabled and init.lsr=0. - 5000 5000 5000 m a i dd,nap device in nap. - 4 4 4 ma i dd,stby device in stby. this is the average for a device in stby with (1) no packets on the channel, and (2) with packets sent to other devices. - 105 100 90 ma i dd,refresh device in stby and refreshing rows at the t ref,max period. - 105 100 90 ma i dd,attn device in attn. this is the average for a device in attn with (1) no packets on the channel, and (2) with packets sent to other devices. - 165 155 140 ma i dd,attn-w device in attn. act command every 8?t cycle , pre command every 8?t cycle , wr command every 4 ? t cycle , and data is 1100..1100 - 575/ 625 b 525/ 580 455/ 500 ma i dd,attn-r device in attn. act command every 8?t cycle , pre command every 8 ? t cycle , rd command every 4 ? t cycle , and data is 1111..1111 c - 490/ 520 450/ 480 400/ 420 ma a. cmos interface consumes power in all power states. b. x16/x18 rdram data width. c. this does not include the i ol sink current. the rdram dissipates i ol ? v ol in each output driver when a logic one is driven. table 16: supply current at initialization symbol parameter allowed range of t cycle v dd min max unit i dd,pwrup,d i dd from power -on to setr 3.33ns to 3.83ns 2.50ns to 3.32ns v dd,min - 150 a 200 b ma i dd,setr,d i dd from setr to clrr 3.33ns to 3.83ns 2.50ns to 3.32ns v dd,min - 250 b 332 b ma
direct rdram ? page 17 k4r271669b/k4r441869b version 1.11 oct. 2000 capacitance and inductance table 17: rsl pin parasitics symbol parameter and conditions - rsl pins min max unit figure l i rsl effective input inductance 4.0 nh figure 62 l 12 mutual inductance between any dqa or dqb rsl signals. 0.2 nh figure 62 mutual inductance between any row or col rsl signals. 0.6 nh d l i difference in l i value between any rsl pins of a single device. - 1.8 nh figure 62 c i rsl effective input capacitance a 800 2.0 2.4 pf figure 62 711 2.0 2.4 600 2.0 2.6 c 12 mutual capacitance between any rsl signals. - 0.1 pf figure 62 d c i difference in c i value between average of {ctm, ctmn, cfm, cfmn} and any rsl pins of a single device. - 0.06 pf figure 62 r i rsl effective input resistance 4 15 w figure 62 a. this value is a combination of the device io circuitry and package capacitances measured at vdd=2.5v and f=400mhz with pin biased at 1.4v . table 18: cmos pin parasitics symbol parameter and conditions - cmos pins min max unit figure l i ,cmos cmos effective input inductance 8.0 nh figure 62 c i ,cmos cmos effective input capacitance (sck,cmd) a 1.7 2.1 pf c i ,cmos,sio cmos effective input capacitance (sio1, sio0) a - 7.0 pf a. this value is a combination of the device io circuitry and package capacitances .
direct rdram ? page 18 k4r271669b/k4r441869b version 1.11 oct. 2000 center-bonded ubga package (62 balls) figure4 shows the form and dimensions of the recom- mended package for the center-bonded csp device class figure 4: center-bonded ubga package table19 lists the numerical values corresponding to dimen- sions shown in figure4. table 19: center-bonded ubga package dimensions a b c d e f g h j 1 2 3 4 5 6 7 d a e1 d e e1 8 e2 top bottom bottom bottom 9 10 11 12 symbol parameter min (128mb/144mb) max (128mb/144mb) unit e1 ball pitch (x-axis) 1.00 1.00 mm e2 ball pitch (y-axis) 0.8 0.8 mm a package body length 11.90 12.10 mm d package body width 10.10 10.30 mm e package total thickness - 1.00 a mm e1 ball height 0.20 0.30 mm d ball diameter 0.30 0.40 mm a. the e,max parameter for so-rimm applications is 0.94mm.

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